1. Field of the Invention
The present invention relates to an information processing apparatus having an instruction prefetch circuit, and more particularly to a microprocessor, including a read-write memory in which a plurality of instructions to be executed are prefetched and a central processing unit (CPU) which executes a program according to the instructions in the read-write memory.
2. Description of the Prior Art
It is well known that in an information processing apparatus (referred to as "microprocessor" hereinafter) the controlability of an execution sequence is one of the important features of a microprocessor. The controlability means the ability to stop the execution of a CPU at an arbitrary address. In a debugging operation of a software development, for example, an operator tries to stop the CPU operation after a predetermined instruction has been executed in order to observe the status of the CPU at the timing when the instruction execution is stopped. Thus, the operator can check the CPU operation and can evaluate the developed software effectively. The stop of the CPU operation is usually called "break" and the address to be stopped is called "break address" or "break point". This break operation is often required in the microprocessor for reasons other than the above-mentioned debugging operation. It is required, for instance, in an interruption operation, a holding operation, a jump operation, a stand-by operation, or the like.
A microprocessor is integrated on a single semiconductor chip and is coupled to an instruction memory chip via a signal bus. The microprocessor sends an address to the instruction memory through the signal bus in a program execution sequence and fetches the accessed instruction in an instruction register provided therein. The fetched instruction is thereafter decoded and is applied to a CPU as control signals. The CPU executes the instruction according to the applied control signals and transfers a result of the execution to a designated device, e.g. a memory, a peripheral equipment, another microprocessor. Thereafter, the microprocessor sends a next address, for accessing a next instruction to be executed, to the instruction memory through the signal bus. A program may be performed by repeating the above described processing steps.
In this case, if the break operation is required at a certain address, a break address at which an instruction execution is to be stopped is preliminarily set in a register means. This register means is coupled to an address comparator which is coupled to the signal bus in order to compare an address transferred to the instruction memory through the signal bus with the break address in the register means. The address comparator generates a break signal when the address or the signal bus coincides with the break address and applies it to the microprocessor. The microprocessor stops an execution of an instruction which will be prearranged in the next step. Thus, in a conventional microprocessor, the break operation has been performed.
Recently, in order to reduce an instruction memory access period and to use a signal bus effectively, an instruction prefetch technique has been proposed. This technique employs the "locality of an instruction" and will be applied to a microprocessor intergrated on a single semiconductor chip. The "locality of an instruction" means that an instruction to be executed next in the series of instructions, which are now being executed, is the instruction which is designated by the address subsequent to the address corresponding to the instruction which is now executing. That is, in a program sequence, the probability is the highest that an instruction designated by the next subsequent address should be the instruction to be executed in the next step. According to this locality of an instruction, a plurality of subsequent instructions can be preliminarily fetched in a microprocessor before an execution of the current instruction is terminated. The prefetch operation can be performed during the current instruction execution by using a signal bus when this bus is an idle state. Program processing speed may be significantly improved by the instruction prefetch technique.
However, if the instruction prefetch technique is applied to a microprocessor, the above-mentioned break operation becomes very difficult and complex since the break address detected by the comparator is different from the address which has been used to designate the instruction now being executed. In other words, when the break signal is generated from the comparator, the microprocessor is executing an instruction which was previously prefetched. This instruction is not the instruction to be stopped by the break signal. Thus, when the break operation is effected in a microprocessor with an instruction prefetch function, the execution of the program is stopped at the address different from the address to be actually stopped.
To avoid this defect, hardware is required for monitoring the CPU operation and the instruction prefetch operation. Further, status information indicating the state of the CPU operation is required and must be taken out of the microprocessor chip. In general, production of the status information is very difficult since the CPU operation sequence is very complex. Therefore, many complex circuits are required and must be added to the microprocessor.